68 lines
1.4 KiB
Markdown
68 lines
1.4 KiB
Markdown
# PR-05 — Gate-Aware Access Path (Choose One, Explicitly)
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### Goal
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Close the loop between Core IR access semantics and VM IR access execution.
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### Choose One Approach (Explicit in PR Description)
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#### Approach A (Preferred)
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* Core IR expresses semantic access:
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* `CoreGateLoadField(field_id)`
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* `CoreGateStoreField(field_id)`
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* Lowering resolves `field_id` → `offset`
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* VM IR emits `GateLoad/GateStore`
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#### Approach B (Minimal)
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* Core IR already carries `offset`
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* Lowering maps directly to `GateLoad/GateStore`
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**Hard rule:** no direct heap access, no fake offsets.
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### Tests
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* Lowering emits correct offsets
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* Offset is visible in VM IR (not implicit)
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---
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# PR-06 — RC Hooks Documentation (No RC Yet)
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### Goal
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Prepare the VM for RC without implementing it yet.
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### Required Changes
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* Document which VM instructions are RC-sensitive:
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* `LocalStore`
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* `GateStore`
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* stack pop / drop (if present)
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* frame end / `FrameSync` as safe points
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* Document RC rules:
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* retain on handle copy
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* release on overwrite/drop
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### Tests
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* Documentation test or unit assertion that the RC-sensitive list exists
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---
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## STOP POINT
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After PR-06:
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* `ir_core` and `ir_vm` are fully decoupled
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* Lowering is deterministic and placeholder-free
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* VM ISA v0 is defined and stable
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* VM runtime work may begin safely
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**Any VM changes before this point must be rejected.**
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