1.4 KiB
1.4 KiB
PR-05 — Gate-Aware Access Path (Choose One, Explicitly)
Goal
Close the loop between Core IR access semantics and VM IR access execution.
Choose One Approach (Explicit in PR Description)
Approach A (Preferred)
-
Core IR expresses semantic access:
CoreGateLoadField(field_id)CoreGateStoreField(field_id)
-
Lowering resolves
field_id→offset -
VM IR emits
GateLoad/GateStore
Approach B (Minimal)
- Core IR already carries
offset - Lowering maps directly to
GateLoad/GateStore
Hard rule: no direct heap access, no fake offsets.
Tests
- Lowering emits correct offsets
- Offset is visible in VM IR (not implicit)
PR-06 — RC Hooks Documentation (No RC Yet)
Goal
Prepare the VM for RC without implementing it yet.
Required Changes
-
Document which VM instructions are RC-sensitive:
LocalStoreGateStore- stack pop / drop (if present)
- frame end /
FrameSyncas safe points
-
Document RC rules:
- retain on handle copy
- release on overwrite/drop
Tests
- Documentation test or unit assertion that the RC-sensitive list exists
STOP POINT
After PR-06:
ir_coreandir_vmare fully decoupled- Lowering is deterministic and placeholder-free
- VM ISA v0 is defined and stable
- VM runtime work may begin safely
Any VM changes before this point must be rejected.