## PR-10 — HIP ABI Freeze v0: Trap Conditions + Debug Surface

### Goal

Freeze the runtime-visible ABI behavior for HIP operations.

### Required Content (Normative)

Add a document (or module-level docs) defining traps:

* Invalid `GateId` → trap `TRAP_INVALID_GATE`
* Dead gate access → trap `TRAP_DEAD_GATE`
* Out-of-bounds offset (`offset >= slots`) → trap `TRAP_OOB`
* Type mismatch (if enforced) → trap `TRAP_TYPE`

Define what a trap includes:

* opcode
* message
* optional span (if debug info is present)

### Required Changes

* Add trap codes/constants in bytecode/VM interface.
* Ensure bytecode format reserves space / structure for propagating trap info.

### Tests (Mandatory)

* Unit tests verifying trap codes are stable (numeric values frozen).
* Doc tests or snapshot for ABI text.

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## PR-11 — Cross-Layer Conformance Tests: Core→VM→Bytecode (HIP)

### Goal

Prove end-to-end determinism and stability.

### Required Tests

1. PBS snippet (or Core IR fixture) that:

* allocates a storage struct
* mutates a field
* peeks value

Assert:

* VM IR contains:

    * `Alloc(type_id, slots)`
    * `GateBeginMutate/EndMutate`
    * `GateStore(offset)`
    * `GateBeginPeek/EndPeek`
    * `GateLoad(offset)`
    * RC ops (retain/release)

2. Bytecode golden output for the same program:

* assert the exact bytes match the frozen ISA/ABI.

### Non-goals

* No runtime execution

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## STOP POINT (Hard Gate)

* HIP access is fully deterministic
* RC events are explicit and testable
* HIP ISA/ABI v0 is frozen with golden bytecode tests

Only after this point may we implement/tune:

* Gate Pool
* Heap allocation
* RC counters + safe point reclaim
* Traps at runtime