# PR-04 — Update `core_to_vm` Lowering (Kill Placeholders)

### Goal

Make lowering the **only** integration point between Core IR and VM IR.

### Required Mapping

* `ir_core::Alloc { ty, slots }`
  → `ir_vm::Alloc { type_id, slots }`

* `BeginPeek / Borrow / Mutate`
  → `GateBegin*`

* `EndPeek / Borrow / Mutate`
  → `GateEnd*`

**Forbidden:**

* `LoadRef(0)`
* `Nop` as semantic replacement

### Tests

* Given a Core IR program with alloc + begin/end, VM IR must contain:

    * shape-explicit `Alloc`
    * correctly paired gate begin/end
    * zero placeholders

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# PR-05 — Gate-Aware Access Path (Choose One, Explicitly)

### Goal

Close the loop between Core IR access semantics and VM IR access execution.

### Choose One Approach (Explicit in PR Description)

#### Approach A (Preferred)

* Core IR expresses semantic access:

    * `CoreGateLoadField(field_id)`
    * `CoreGateStoreField(field_id)`
* Lowering resolves `field_id` → `offset`
* VM IR emits `GateLoad/GateStore`

#### Approach B (Minimal)

* Core IR already carries `offset`
* Lowering maps directly to `GateLoad/GateStore`

**Hard rule:** no direct heap access, no fake offsets.

### Tests

* Lowering emits correct offsets
* Offset is visible in VM IR (not implicit)

---

# PR-06 — RC Hooks Documentation (No RC Yet)

### Goal

Prepare the VM for RC without implementing it yet.

### Required Changes

* Document which VM instructions are RC-sensitive:

    * `LocalStore`
    * `GateStore`
    * stack pop / drop (if present)
    * frame end / `FrameSync` as safe points

* Document RC rules:

    * retain on handle copy
    * release on overwrite/drop

### Tests

* Documentation test or unit assertion that the RC-sensitive list exists

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## STOP POINT

After PR-06:

* `ir_core` and `ir_vm` are fully decoupled
* Lowering is deterministic and placeholder-free
* VM ISA v0 is defined and stable
* VM runtime work may begin safely

**Any VM changes before this point must be rejected.**