pr2.2
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8b744a120e
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@ -257,10 +257,7 @@ impl VirtualMachine {
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let mut steps_executed = 0;
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let mut ending_reason: Option<LogicalFrameEndingReason> = None;
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while (self.cycles - start_cycles) < budget
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&& !self.halted
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&& self.pc < self.program.rom.len()
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{
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while (self.cycles - start_cycles) < budget && !self.halted && self.pc < self.program.rom.len() {
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// Debugger support: stop before executing an instruction if there's a breakpoint.
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// Note: we skip the check for the very first step of a slice to avoid
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// getting stuck on the same breakpoint repeatedly.
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@ -272,27 +269,6 @@ impl VirtualMachine {
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let pc_before = self.pc;
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let cycles_before = self.cycles;
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// Fast-path for FRAME_SYNC:
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// This instruction is special because it marks the end of a logical game frame.
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// We peak ahead to handle it efficiently.
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let opcode_val = self.peek_u16()?;
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let opcode = OpCode::try_from(opcode_val)?;
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if opcode == OpCode::FrameSync {
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self.pc += 2; // Advance PC past the opcode
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self.cycles += OpCode::FrameSync.cycles();
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steps_executed += 1;
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ending_reason = Some(LogicalFrameEndingReason::FrameSync);
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break;
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}
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if opcode == OpCode::Trap {
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self.pc += 2; // Advance PC past the opcode
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self.cycles += OpCode::Trap.cycles();
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steps_executed += 1;
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ending_reason = Some(LogicalFrameEndingReason::Breakpoint);
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break;
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}
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// Execute a single step (Fetch-Decode-Execute)
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if let Err(reason) = self.step(native, ctx) {
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ending_reason = Some(reason);
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@ -433,7 +409,9 @@ impl VirtualMachine {
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}
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}
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OpCode::Trap => {
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// Handled in run_budget for interruption
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// Manual breakpoint instruction: consume cycles and signal a breakpoint
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self.cycles += OpCode::Trap.cycles();
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return Err(LogicalFrameEndingReason::Breakpoint);
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}
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OpCode::PushConst => {
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let idx = instr
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@ -994,7 +972,9 @@ impl VirtualMachine {
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}
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}
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OpCode::FrameSync => {
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return Ok(());
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// Marks the logical end of a frame: consume cycles and signal to the driver
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self.cycles += OpCode::FrameSync.cycles();
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return Err(LogicalFrameEndingReason::FrameSync);
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}
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}
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@ -1,54 +1,3 @@
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# PR-2.2 — Simplify VM Execution Loop (Pure Stack Machine)
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### Briefing
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The VM should operate as a simple stack-based interpreter with a clear fetch–decode–execute loop, without hidden side channels or legacy behaviors.
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### Target
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* Normalize the VM main loop to a clean stack-machine structure.
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* Remove any legacy control paths tied to HIP/RC behavior.
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### Work items
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* Refactor the main interpreter loop to:
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* Fetch instruction at PC.
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* Decode opcode.
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* Execute operation on stack/frames.
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* Remove any conditional logic that depends on HIP/RC state.
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* Ensure PC advancement is canonical and centralized.
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### Acceptance checklist
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* [ ] VM loop is structurally simple and readable.
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* [ ] No HIP/RC conditionals remain.
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* [ ] VM compiles and runs basic programs.
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* [ ] `cargo test` passes.
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### Tests
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* Existing tests only.
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### Junie instructions
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**You MAY:**
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* Refactor the interpreter loop for clarity.
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* Remove legacy conditionals.
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**You MUST NOT:**
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* Change opcode semantics.
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* Introduce GC, closures, or coroutines here.
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* Redesign the instruction set.
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**If unclear:**
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* Ask before modifying control flow assumptions.
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---
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# PR-2.3 — Normalize Value Model (Stack vs Heap References)
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### Briefing
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